ASIC Engineering Technical Leader - Design Verification Job at Cisco Systems
What You’ll Do
Cisco COG team is looking for an expert and versatile Senior ASIC Design Engineer. You will have an ASIC design background with experience in design, physical design, post silicon validation, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.
The role expects you to be specifically responsible for the Design and Static Verification of the chip, which includes :
Static Timing Analysis, developing Timing Constraints, understanding the top-level design and vendor IPs/PLLs/Serdes/PHY Macros and all aspects of timing modes including(design for testing) DFT timing.
Analysis of cross clock domain paths at Full chip level and experience with CDC analysis tools.
Drive the Formal verification flow including Logic Equivalence Check (LEC) flow using Formal tools like Formality or other equivalent tools .
Document and improve methodologies to make product successful.
Design and verify of SoC ASIC.
Work closely with the physical back-end team on synthesis, DFT, STA.
Who You'll Work With
You will be working with a dedicated and energetic team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement.
In terms of design responsibilities, you will be working with our system team for Micro architecture define, design implementation, and design verification, and with our backend team for chip integration and verification.
Who You Are
Worked in micro-architecture and design of high-scale, high-performance ASICs.
Validated experience in implementation: specification, design, formal verification, system testing.
Validated experience in physical design aspects: timing analysis and closure, CDC analysis, power/area optimizations, macro size/placement analysis.
Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
Experience with expertise in the digital SOC COT design flow based on the advanced technology nodes(e.g. 7nm,5nm CMOS).
Expertise in chip integration, including chip floor planning, synthesis, DFT.
Expertise in verification, including function verification, formal verification, and gate-level verification
Knowledge of SV/UVM based verification.
In depth knowledge of generic digital logic design, such as FIFO, FSM, cross-clock domain logics.
Strong scripting, debugging and problem solving skills.
Minimum Qualifications
BS/MS in Electrical Engineering
8+ working experience in the field of digital ASIC Design
Understands all aspects of implementation: specification, design, timing-closure, power-optimization, and flow automation.
Experienced in system debug and SW/HW bringup.
RTL and Synthesis experience.
Synthesis and Block/Full chip STA constraints and Timing analysis
Experience with PrimeTime and Spyglass CDC (or equivalent tools)
End-to-end design experience from Verilog to gates, block planning, area/timing closure is helpful.
Programming/scripting skills (C, Perl)
Good written/verbal interpersonal skills and leadership skills.
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Cisco COG team is looking for an expert and versatile Senior ASIC Design Engineer. You will have an ASIC design background with experience in design, physical design, post silicon validation, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.
The role expects you to be specifically responsible for the Design and Static Verification of the chip, which includes :
Static Timing Analysis, developing Timing Constraints, understanding the top-level design and vendor IPs/PLLs/Serdes/PHY Macros and all aspects of timing modes including(design for testing) DFT timing.
Analysis of cross clock domain paths at Full chip level and experience with CDC analysis tools.
Drive the Formal verification flow including Logic Equivalence Check (LEC) flow using Formal tools like Formality or other equivalent tools .
Document and improve methodologies to make product successful.
Design and verify of SoC ASIC.
Work closely with the physical back-end team on synthesis, DFT, STA.
Who You'll Work With
You will be working with a dedicated and energetic team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement.
In terms of design responsibilities, you will be working with our system team for Micro architecture define, design implementation, and design verification, and with our backend team for chip integration and verification.
Who You Are
Worked in micro-architecture and design of high-scale, high-performance ASICs.
Validated experience in implementation: specification, design, formal verification, system testing.
Validated experience in physical design aspects: timing analysis and closure, CDC analysis, power/area optimizations, macro size/placement analysis.
Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
Experience with expertise in the digital SOC COT design flow based on the advanced technology nodes(e.g. 7nm,5nm CMOS).
Expertise in chip integration, including chip floor planning, synthesis, DFT.
Expertise in verification, including function verification, formal verification, and gate-level verification
Knowledge of SV/UVM based verification.
In depth knowledge of generic digital logic design, such as FIFO, FSM, cross-clock domain logics.
Strong scripting, debugging and problem solving skills.
Minimum Qualifications
BS/MS in Electrical Engineering
8+ working experience in the field of digital ASIC Design
Understands all aspects of implementation: specification, design, timing-closure, power-optimization, and flow automation.
Experienced in system debug and SW/HW bringup.
RTL and Synthesis experience.
Synthesis and Block/Full chip STA constraints and Timing analysis
Experience with PrimeTime and Spyglass CDC (or equivalent tools)
End-to-end design experience from Verilog to gates, block planning, area/timing closure is helpful.
Programming/scripting skills (C, Perl)
Good written/verbal interpersonal skills and leadership skills.
Please Note :
clarksqn.com is the go-to platform for job seekers looking for the best job postings from around the web. With a focus on quality, the platform guarantees that all job postings are from reliable sources and are up-to-date. It also offers a variety of tools to help users find the perfect job for them, such as searching by location and filtering by industry. Furthermore, clarksqn.com provides helpful resources like resume tips and career advice to give job seekers an edge in their search. With its commitment to quality and user-friendliness, Site.com is the ideal place to find your next job.